555 NE555 LM555 Timer IC

Timing from microseconds to hours
Actable or nonstable operation
Adjustable duty cyclist-compatible output can sink or source up to 200 ma
Ttl-compatible output can sink or source up to 200 ma

These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of vcc. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (reset) input can override all other inputs and can be used to initiate a new timing cycle. When reset goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (disch) and ground. The output circuit is capable of sinking or sourcing current up to 200 ma. Operation is specified for supplies of 5 v to 15 v. With a 5-v supply, output levels are compatible with ttl inputs.