74139 Dual 2 to 4 line Decoder / Demultiplexer IC DIP-16

• Designed specifically for high speed: Memory decoders Data transmission systems

• 74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers

• Schottky clamped for high performance

• Typical propagation delay (3 levels of logic) is 21 ns

• Typical power dissipation  is 34 mW

The 74LS139 comprises two separate two-line-to-four line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.