CD4017 Counter IC

Medium speed operation,,,10 mhz (typ,) At vdd = 10 standardized, symmetrical output characteristics
Medium speed operation,,,10 mhz (typ,) At vdd = 10 v
Standardized, symmetrical output characteristics

Cd4017b 5-stage Johnson counters having 10 decoded output. Inputs include a clock, a reset, and a clock inhibit signal. Schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the clock inhibit signal is low. Counter advancement via the clock line is inhibited when the clock inhibit signal is high. A high reset signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A carry-out signal completes on cycle every 10 clock input cycles in the cd4017b and is used to ripple-clock the succeeding device in a multi-device counting chain